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Data Sheet
CURRENT CHANNEL ADC
Figure 41 shows the ADC and signal processing path for the
input IA of the current channels (same for IB and IC). In
waveform sampling mode, the ADC outputs are signed twos
complement 24-bit data-words at a maximum of 26.0 kSPS
(thousand samples per second). With the specified full-scale
analog input signal of ±0.5 V, the ADC produces its maximum
output code value (see Figure 41). This diagram shows a full-
scale voltage signal being applied to the differential inputs IAP
and IAN. The ADC output swings between 0xD7AE14
ADE7758
When in waveform sample mode, one of four output sample
rates can be chosen by using Bit 5 and Bit 6 of the WAVMODE
register (DTRT[1:0]). The output sample rate can be 26.04 kSPS,
13.02 kSPS, 6.51 kSPS, or 3.25 kSPS. By setting the WFSM bit in
the interrupt mask register to Logic 1, the interrupt request
output IRQ goes active low when a sample is available. The
timing is shown in Figure 40 . The 24-bit waveform samples are
transferred from the ADE7758 one byte (8-bits) at a time, with
the most significant byte shifted out first.
IRQ
(?2,642,412) and 0x2851EC (+2,642,412).
SCLK
READ FROM WAVEFORM
Current Channel Sampling
The waveform samples of the current channel can be routed to
DIN
DOUT
0
0x12
SGN
the WFORM register at fixed sampling rates by setting the
WAVSEL[2:0] bit in the WAVMODE register to 000 (binary)
(see Table 20). The phase in which the samples are routed is set
by setting the PHSEL[1:0] bits in the WAVMODE register.
Energy calculation remains uninterrupted during waveform
sampling.
GAIN[4:3]
CURRENT CHANNE L DATA–24 BITS
Figure 40. Current Channel Waveform Sampling
The interrupt request output IRQ stays low until the interrupt
routine reads the reset status register (see the Interrupts section ) .
2.42V, 1.21V, 0.6V
REFERENCE
GAIN[7]
CURRENT RMS (IRMS)
CALCULATION
IAP
GAIN[1:0]
×1, ×2, ×4
DIGITAL
INTEGRATOR 1
WAVEFORM SAMPLE
REGISTER
V IN
IAN
PGA1
ADC
HPF
ACTIVE AND REACTIVE
POWER CALCULATION
CHANNEL 1 (CURRENT WAVEFORM)
DATA RANGE AFTER INTEGRATOR
50Hz
(50Hz AND AIGAIN[11:0] = 0x000)
0x34D1B8
0.5V/GAIN
0.25V/GAIN
0.125V/GAIN
V IN
0x2851EC
CHANNEL 1
(CURRENT WAVEFORM)
DATA RANGE
0x000000
0xCB2E48
0V
0x000000
60Hz
CHANNEL 1 (CURRENT WAVEFORM)
DATA RANGE AFTER INTEGRATOR
(60Hz AND AIGAIN[11:0] = 0x000)
ANALOG
INPUT
RANGE
0xD7AE14
ADC OUTPUT
WORD RANGE
0x2BE893
0x000000
1 WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS
ATTENUATED DEPENDING ON THE SIGNAL FREQUENCY BECAUSE THE
INTEGRATOR HAS A –20dB/DECADE FREQUENCY RESPONSE. WHEN DISABLED,
THE OUTPUT WILL NOT BE FURTHER ATTENUATED.
Figure 41. Current Channel Signal Path
Rev. E | Page 19 of 72
0xD4176D
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